library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity int_rom is
port(
		clk      : in  std_logic;
		rst      : in  std_logic;
		rd       : in  std_logic;
		addr     : in  std_logic_vector (15 downto 0);
		data     : out std_logic_vector (7 downto 0)
);
end int_rom;

architecture Behavioral of int_rom is
	type rom_type is array (0 to 4095) of STD_LOGIC_VECTOR (7 downto 0);
	constant PROGRAM : ROM_TYPE := (

--Add Acc, #10101010
"00100100",
"10101010",
--
--LCALL 10101010 11111111
"00010010",
"10101010",
"11111111",

	-- Old Testing Code --
	"00100101", -- ADD ACC,direct
	"01010101", -- direct Address
	"00100100", -- ADD ACC,#data
	"00100010", -- #data
	"00000000", -- NOP
	"00100100", -- ADD ACC,#data
	"01000100", -- #data
	"00000000", -- NOP
	"00100100", -- ADD ACC,#data
	"10001000", -- #data
	"00000000", -- NOP
	"00110111",	-- ADDC A, @R1   	, **C, AC is expected
					--"00000001", in Bank0, ((R1))
	--"00110111", -- ADDC A, @R1		, **C, AC is expected
					--"00000001", in Bank0, ((R1))
	"10010111", -- SUBB A, @R1		, **C, AC is expected
					--"00000001", in Bank0, ((R1))
	"00111000", -- ADDC ACC,Rn 		, **C, AC is expected
					--"00000001", -- (Rn) 
	"00000100",	-- INC A
	"00010100",	-- DEC A
	"00001000", -- INC R0(bank0)
	"00101000", -- ADD R0(bank0)
	"10011000", -- SUBB R0(bank0)
	"00011000", -- DEC R0(bank0)
	"00000000", -- NOP
	"00100100", -- ADD ACC,#data
	"00010001", -- #data
	"00100100", -- ADD ACC,#data
	"00010001", -- #data
	"11101001", --LABEL1: MOV A,R1
	"00100100", --ADD A,#01H
	"00000001",
	"11111001", --MOV R1,A
	"10111001", --CJNE R1,#04H,LABEL1
	"00000100",
	"11111001",
	"10001001", --MOV 90H,R1
	"10010000",
	others => "00000000"
);

	begin

	process (rst, rd, addr)
	begin
		if( rst = '1' ) then
			data <= "--------";
		elsif( rd = '1' ) then
			data <= PROGRAM(conv_integer(addr));
		else
			data <= "--------";
		end if;
	end process;
end Behavioral;
